Pablo Huerta focuses on all aspects of patent counseling and patent prosecution in relation to a wide variety of electrical and computer-related technologies. Pablo leverages years of experience, both as a patent examiner and an engineer to bring value to his clients in managing their patent portfolios.
Pablo has in-depth knowledge of the workings of the U.S. Patent and Trademark Office (USPTO) and understands how to move an application through the process. Pablo worked as a patent examiner for five years and developed a solid foundation in the field of solid-state memory, including read/write circuitry, semiconductor structures, and programming methods for NAND flash, MRAM, and phase-change memory.
Pablo also worked as an engineer in high tech for more than twelve years. At Sun Microsystems, he managed the product quality of network storage devices, including NAS appliances and other RAID implementations. Pablo developed test processes for isolating hardware defects in manufacturing, and liaised closely with design teams, suppliers, and external manufacturers to debug and finalize product designs. At Novellus Systems, Pablo managed design projects for semiconductor PVD sputtering equipment. He developed a solid technical understanding of semiconductor process technology and was recognized for his diligence in resolving electrical design issues.
Pablo is fluent in Spanish and has endeavored in the study of French, Italian, and Mandarin Chinese.
* Admitted only in MD. Practice limited to matters and proceedings before federal courts and agencies.
- Received Outstanding Performance Award in engineering for resolving electrical grounding issues that affected PVD sputtering equipment at customer locations worldwide.
- As a legal intern, performed legal research relating to high-tech crime at the San Francisco District Attorney’s Office; and assisted pro bono clients with immigration matters at the Katherine & George Alexander Community Law Center.
- In law school, received CALI awards for highest grade in Legal Research and Writing, Advanced Legal Writing, and Civil Clinical Skills.
- U.S. Patent and Trademark Office
- Santa Clara University School of Law, J.D., June 2010
- California Polytechnic State University, San Luis Obispo, B.S., Electrical Engineering, June 1995
- Author. “USPTO Extends Certain Deadlines for Delays Related to COVID-19,” BoMc Blog, April 13, 2020.
- Author. “Federal Circuit Clarifies the Test for Eligibility of Software Inventions Under Section 101,” BoMc Blog, December 17, 2019.
- Author. “Federal Circuit Weighs in on Limiting Effect of Preamble,” BoMc Blog, January 3, 2018.
- American Intellectual Property Law Association (AIPLA), Member